In semiconductor devices, for instance Systems on a Chip (SoC), a clock signal typically needs to be generated for many applications and functions. Conventionally, phase locked loop (PLL's) are used for clock generation in bigger SoCs as they faithfully multiply a reference crystal clock to a stable high frequency clock. The negative feedback loop in PLL's generates a supply, temperature and process in-sensitive clock with very small frequency spread. However, in smaller systems with limited PAD/PIN, PLL's are not cost effective solution as they need an external reference crystal clock. So, one possibility is to use a reference oscillator in a negative feedback loop to mimic the PLL performance.
As the on chip resistors and capacitors vary across process, frequency of the oscillator may also vary significantly affecting the system performance. All digital systems process and manipulate only digital codes consisting of 0's and 1's. Since typically the output frequency of the voltage controlled oscillator (VCO) is controlled by an analog input voltage, a digital to analog converter (DAC) is usually used to convert trimming bits to an analog voltage and then to program the frequency. A conventional DAC implementation scheme may consume almost 70-80% area of the oscillator and also the DAC power consumption may become an over head to the overall system.
In common VCO implementations, a negative feedback loop may be used to linearize the VCO. But any mismatch between control voltage (Vctl) and reference voltage (Vref) can lead to non-linearity.
US 2012/0074986 A1 discloses a generation of a clock signal. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency.
Thus, there may be a need for an improved oscillator arrangement being insensitive to temperature and voltage variations.